Angel SITAEL 15/2023 - Senior Digital and FPGA Designer Invia

MISSION

The SeniorDigital Design Engineer is involved in development of digital unit and sub-system for space applications, in accordance to customer or internal requirements and applicable standards (such as ECSS), supported by analysis (for instance radiation, FMEA/FDIR, thermal, etc.). The design activity has to be conducted in multidisciplinary team in a scenario where requirements are all closely related to each other and technical compromises have to be readily identified.

RESPONSIBILITIES

• Design of digital system based on FPGA for space applications;
• Design of digital system based on FPGA for electrical ground support equipment;
• Interface with Analog designers for model development, integration and test of avionic equipment;
• Test of digital design system (up to engineering model level);
• Writing technical documentation

TECHNICAL SKILLS / REQUIREMENTS

Experience in digital electronics, in particular design of digital system, design with embedded microcontroller, Hardware Design with digital components, interfaces with Spacecraft subsystems (such as microcontroller, FPGA, ADC, DAC, etc), FMEA and radiation analysis

• Master's degree in Engineering is requested, 
• Minimum of 3 years of professional experience with state-of-the-art EDA software tools for digital IC;
• Excellent understanding of digital and FPGA circuit design: VHDL/System Verilog;
• Digital IP, implementation, integration and verification;
• Experience with clock systems and multiple asynchronous clock domains;
• Experience with FPGA devices as Xilinx and Microsemi;
• Experience with Libero SoC, Vivado, and Mentor ModelSim/QuestaSim;
• Experience in the implementation of IP blocks based on interface requirements
• Programming skills and scripting (e.g. Python, TCL);
• Ability to analyze system requirements in order to define features to be implemented in Hardware
• Experience in SoC architecture definition
• Knowledge of test-bench definition for requirements verification
• Knowledge of EDA tool for code coverage analysis.
• Knowledge of Static Timing Analysis and constraints definition for timing closure
• Knowledge of advanced Laboratory Instrumentation (e.g. Oscilloscope, Logical Analyzer, Spectrum Analyzer) in order to validate digital solution

LOCATION

Pisa